Postponed to 2021

Hours:
20 hours (5 credits)

Room:
Aula Riunioni del Dipartimento di Ingegneria dell’Informazione, Via G. Caruso 16, Pisa – Ground Floor

Short Abstract:
Virtually all digital IC platforms today are based on flexible programmable processor cores, with a trend towards Multi/Manycore architectures comprising 10-100 cores. This trend is imposed by high performance and power/energy efficiency demands. Specifically in competitive embedded application domains like smartphones, wireless infrastructure, and automotive, there are tight efficiency constraints on power, energy, timing, design cost, and production cost of the underlying HW platforms. The need for flexibility and efficiency leads to heterogeneous platform architectures, composed of off-the-shelf (yet partially customizable) IP cores, like RISCs, and custom application-specific processors, such as DSP or security accelerators. Moreover, these cores communicate over complex on-chip interconnect and memory subsystem architectures. These trends impose huge challenges for ICT system and semiconductor industry. Novel design methodologies and tools are required for managing the skyrocketing HW platform design complexity, while simultaneously optimizing systems and components for performance, power, and costs. Furthermore, migrating legacy application software code or firmware as well as developing and debugging new software for highly parallel HW platforms causes a significant design productivity gap. This course presents various advanced system-level design methodologies in a practice-oriented way, intended to enable industrial embedded systems engineers to manage the complexity of current and future HW/SW multicore devices and to achieve predictable and competitive results in shorter time. Topics include: Software compilation techniques, System-on-Chip design methodology, power optimization, Virtual Prototyping and simulation, and Application Specific Processor Design. Furthermore, a brief outlook on hardware security issues will be provided.

Course Contents in brief:

• Multiprocessor Systems-on-Chip
• Electronic System Level Design
• SoC architecture exploration and power estimation
• Virtual Prototyping
• Multicore programming tools
• Application-specific processing elements (ASIPs)

Schedule:

Postponed to 2021