Hours:
16 hours (4 credits)

Room:

Aula Riunioni del Dipartimento di Ingegneria dell’Informazione, Via G. Caruso 16, Pisa - Ground Floor

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Short Abstract:

The course focuses on ultra-low power integrated circuit design for distributed and decentralized systems (e.g., IoT, AIoT), and in particular on the design of chips for edge nodes. The course provides an insight into system requirements imposed by real-world applications, the fundamentals to understand the related challenges, and advanced design ideas to address them. Several aspects are discussed from a design viewpoint, ranging from ultra-low power system architectures, architectures and circuits for processing, data sensemaking (e.g., machine learning on a chip), energy harvesting, on-chip power conversion, sensor interfaces and wireless communications.
The course is structured into three sections. In the first one, fundamentals on ultra-low power and minimum-energy design are provided as common background. Key concepts, models and techniques are presented to enable intelligent systems with divergently high peak performance and low minimum power, as relevant to current and prospective applications of distributed/decentralized systems. In the second section, recent techniques that drastically extend the performance-power scalability of intelligent systems are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for the entire signal chain from sensors to sensemaking. Demonstrations include the data and the clock path of the digital subsystem, the analog sub-system and power management. Energy-quality scaling is explored as additional dimension to break the conventional performance-energy tradeoff in error-resilient applications such as AI and vision, from networks on chip to memories and accelerators. Further performance and energy improvements are discussed through uncommonly flexible in-memory broad-purpose computing frameworks for true data locality, from buffering to signal conditioning and neural net workloads. In the third section, adaptation to an even wider range of powerperformance targets is presented to shrink and eventually suppress batteries as fundamental obstacle to overcome in the exponential scaling towards trillions of devices (environmental,
economics, logistics). Sensor interfaces, processors and wireless transceivers fitting existing infrastructure (e.g., WiFi) with power reductions by orders of magnitude are discussed and exemplified by numerous silicon demonstrations, and their system integration.
In this course, all design principles are exemplified by silicon demonstrations from the state of the art, and with extensive measurement results from our research group to closely mimic the learning experience in a lab environment. As further learning tool, databases of commercial products and state-of-the-art research prototypes are introduced and offered to the attendees to understand the trends, the requirements and the advances taking place in the field. The lecture notes are complemented by springer books available in most university libraries in electronic form to extend the learning journey beyond the course. The attendees should have some basic understanding of electronic circuits and integrated circuits and/or systems.

Course Contents in brief:

1. SECTION I: Fundamentals of ultra-low power design for intelligent self-powered systems
2. SECTION II: Design frameworks and techniques for aggressive power-performance tradeoff extension
3. SECTION III: Green and alert integrated systems without battery for environmental, technological, economic and logistic sustainability towards the trillion scale

Schedule:

1. Day1 20/06/2022 – 9:00-15:30 (6 hours): megatrends and perspectives on distributed/decentralized systems, requirements, recap of circuit models, design for nearlyminimum energy operation.
2. Day2 21/06/2022 – 9:00-15:30 (6 hours): background on power-performance tradeoff in intelligent and always-on systems, techniques to extend of power-performance range beyond voltage scaling from data path to clock path, energy-quality scaling and application to main sub-systems, in-memory computing, case studies.
3. Day3 22/06/2022 – 9:00-14:00 (4 hours): trends and need for battery suppression (environment, economics), integrated energy sources, system powering/activation schemes, battery-indifferent and battery-less system architectures, circuit techniques for main sub-systems, case studies.