Modern networks have critical security needs and a suitable level of protection and performance is usually achieved with the use of dedicated hardware cryptographic cores. Although the Advanced Encryption Standard (AES) is considered the best approach when symmetric cryptography is required, one of its main weaknesses lies in its measurable power consumption. Side Channel Attacks (SCAs) use this emitted power to analyze and revert the mathematical steps and extract the encryption key. In this work we propose a simulated methodology based on Correlation and Differential Power Analysis. Our solution extracts the simulated power from a gate-level implementation of the AES core and elaborates it using mathematical-statistical procedures. An SCA countermeasure can then be evaluated without the need for any physical circuit. Each solution can be benchmarked during an early step of the design thereby shortening the evaluation phase and helping designers to find the best solution during a preliminary phase. The cost of our approach is lower compared to any kind of analysis that requires the silicon chip to evaluate SCA protection.