Random numbers are widely employed in cryptography and security applications, and they represent one of the main aspects to take care of along a security chain. They are employed for creation of encryption keys, and if generation process is weak, the whole chain can be compromised: weaknesses could be exploited to retrieve the key, thus breaking even the strongest cipher. This paper presents the architecture of a digital Random Number Generator (RNG) IP-core to be employed as hardware accelerator for cryptographically secure applications. Such design has been developed starting from specifications based on literature and standards, and in order to assess the randomness degree of generated output, it has been successfully validated through the official NIST Statistical Test Suite. Finally the RNG IP-core has been characterized on Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies: on Intel Stratix IV FPGA it offers a throughput of 720 Mbps requiring up to 6000 Adaptive Logic Modules (ALMs), while on Silvaco PDK 45nm Open Cell Library it reaches a throughput of 4 Gbps with a complexity of 119 kGE.

Keywords: cryptographic HW accelerators, IP-core, on-chip random number generator, cybersecurity, FPGA, ASIC standard-cell, NIST