SpaceWire standard is the State-Of-The-Art for spacecraft On-Board-Data-Handling (OBDH) communication, defined by the European Space Agency (ESA) and adopted in numerous missions worldwide (e.g., Rosetta, BepiColombo, Mars Express, JWST). The development of SpaceWire compliant devices requires a specific set of test equipment instrumentation, to verify the correct functionality of SpaceWire units under test. Among such equipment, link monitoring analyzers (i.e., “sniffers”) are essential tools to verify data traffic generated over SpaceWire links. Despite unobtrusive link monitoring is a very recurrent need, the complexity of each specific scenario makes it challenging to run accurate tests with the currently available solutions on the market. The existing devices are usually limited in the eventtriggered analysis, lacking an efficient way to capture exact events occurrences, i.e., in presence of sporadic events causing nondeterministic faults of the system under test. This paper presents the design of an embedded architecture for a SpaceWire Network sniffer, implemented on a System on Chip (SoC) device, comprising of a dual-core CPU unit, aided by programmable logic resources of a Field Programmable Gate Array (FPGA). The proposed solution aims at offering an easy-to-use SpaceWire Link Analyzer, with advanced trigger chain-able conditions and postprocessing capabilities, to empower SpaceWire device developers to test and verify their work with deserved accuracy and effectiveness.

Keywords: SpaceWire; Link Analyzer; Sniffer; Electrical Ground Support Equipment (EGSE); test equipment; On-BoardData-Handling (OBDH); spacecraft communications; serial communications