Abstract: SpaceWire (SpW) devices are widely used in space applications on-board satellites. Their verification is fundamental because it ensures that the Design Under Test (DUT) is bug-free, without the risk of compromising an entire space mission.
In this paper an innovative architecture of a Verification Intellectual Property (VIP) based on Universal Verification Methodology (UVM) for the testing of a SpW Codec IP core is presented. Its core is the Twin Model, developed in SystemVerilog and compliant with UVM, which emulates the ideal behavior of the SpW Codec. It communicates directly with the DUT through the Data-Strobe interface with the advantage of automatically generating and sending the data needed to create and maintain the link and leaving only the definition of the payload data to be transmitted to the user. Other two Twin Models are used to create a secondary communication link, named Twin Link, in parallel with the main one. This is the best solution to verify the correct behavior of the DUT in case of errors on the link. In fact, since the Twin Link emulates the ideal communication link behavior, it provides a benchmark for verifying the one including the DUT. A specific functional block is designed to inject on the link all types of errors defined by the standard. The result is a highly reliable and configurable VIP that allows for automatic testing of all the functionalities of any SpW codec. Finally, a full verification campaign was performed with two different DUTs, achieving 100% functional coverage.

Keywords: Universal Verification Methodology (UVM), Space-Wire (SpW) Codec, Verification IP, Twin Model, Twin Link, Verification Environment, functional verification, reusability, SystemVerilog.