As of today, designing Current References (CRs) with enhanced PVT-robustness is still hardly straightforward, especially under area occupation constraints. In this work, we present a novel beta-multiplier CR, performing first-order temperature compensation without the need of separate positive and negative Temperature Coefficient (TC) current generators. At the design stage, the reference current temperature dependency can be tuned by acting on the area distribution among matched transistors with asymmetrical body effects. Electrical simulations of a 949-nA 0.18-µm CMOS design show TC, line sensitivity and relative standard deviation values equal to 258 ppm/°C, 4.59%/V and 1.24%, respectively, with a 0.033 mm² layout. Such findings validate the proposed approach as a reliable temperature compensation strategy, comparable with the state of the art.

Keywords: beta multiplier, body effect, current reference, temperature compensation, process compensation

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