Modern computing platforms exploiting Coarse-Grained Reconfigurable Array architectures depend highly on the efficiency with which data are handled inside the architecture. Moving data is critical in computing-intensive systems to maximize energy efficiency and reduce latency. Access to the main memory is the most costly operation; therefore, the data retrieved must be kept near the processing elements of the architecture as long as possible to reduce data transfers. Modern algorithms involve very different access patterns to the main memory, requiring high versatility for Direct Memory Access (DMA) mechanisms. This work presents the SmartDMA architecture, a RISC-V-based programmable DMA controller specifically designed to perform adaptable memory access patterns and implement proper data reuse policies in CGRA-based systems. It comprises a set of Data Mover Engines (DMEs) that implement configurable 1D, 2D, and 3D data movements. Using a custom RISC-V ISA extension and a programmable event network, the application-specific firmware loaded on the SmartDMA can schedule DMA commands among all DMEs, ensuring that they are always busy with data transactions. We show a typical use case that takes advantage of CGRA-based processing and highlights the functionality of the SmartDMA. We synthesized the SmartDMA on TSMC 40nm low-power standard-cell technology at 350 MHz for three architectural configurations, increasing the number of DMEs, with a maximum memory throughput of 5.6 GB/s: small, medium, and large. The small configuration occupies 46.2k um2 of cell area and consumes 8.64 mW. The medium occupies 117k um2 and consumes 23.1 mW. The large one occupies 243k um2 and consumes 42.7 mW.

Keywords: DMA Controller, RISC-V, custom ISA, CGRA, adaptable memory access, 2D-3D data movement, data intensive, compute intensive.

File: https://doi.org/10.36227/techrxiv.172833678.84362825/v1