Field Programmable Gate Arrays find extensive use across various domains, ranging from telecommunications to Machine Learning tasks. In the context of space applications, they emerge as a highly favourable choice, owing to their high degree of flexibility and their accessibility in different silicon-grade technologies. However, due to the high associated costs of radiation-hardened devices, the prevalence of radiation-tolerant devices is more common in practical deployment scenarios. In this sense, robustness-enhancing techniques can still be applied, thus allowing the employment of these devices in long-duration tasks without the need for a radiation-hardened counterpart. In this paper, we propose a modelling approach for estimating the reliability of a digital design system in space before carrying out fault injection tests and radiation campaigns. For this purpose, we employ a high-level tool called Möbius to obtain a first reliability estimation against Single Event Upsets by means of Fault Tree Models. We also propose a novel methodology for defining which fault mitigation techniques should be applied to each design sub-module, considering the most commonly used in the space environment. In particular, we focus on a specific use case, namely a Soft Graphic Processing Unit IP, implemented on the Xilinx RT XQRKU060 FPGA. We analyze the criticality, power and area impact of the most important design parts of the GPU when implemented in hardware, introducing a classification approach for associating an appropriate fault mitigation technique with each of them. Finally, in the last section of the paper, we hint at future development and conclude the work.

Keywords: Field Programmable Gate Array, Single Event Upsets, Soft GPU, Reliability, Space, Modelling, Criticality, Fault Mitigation