ABSTRACT - In recent years, optical communications have gained a foothold in satellite communications because of their high bandwidth data transmission capability and the capacity to cover much greater distances than radio systems. Recently, the Consultative Committee for Space Data Systems (CCSDS) has defined a standard for two different optical signallings for satellite communications: the High Photon Efficiency (HPE), designed for atmospheric channels in photon-starved regime, and the Optical On-Off Keying (O3K) for high photon flux regime. Due to the target applications, the verification of the digital design is particularly strict and requires a complex verification environment able to completely test the so-called Device Under Test (DUT) in all its functional aspects.
This paper presents a Verification Environment for the testing of both HPE and O3K Encoder IP cores. It is based on two Twin Models which emulate the ideal behavior of HPE and O3K Encoders, respectively. According to the coding standard to be applied, only one of them is instantiated within the environment and stimulated with the same inputs of the DUT, providing the expected outputs. Both the Verification Environment and the Twin Models have been developed in SystemVerilog Hardware Verification Language (HVL) and are fully compliant with the Universal Verification Methodology (UVM), which represents the actual state-of-the-art for functional verification. This provides significant advantages in terms of reusability and maintainability.
The result is a highly reliable, user-friendly, and configurable Verification Environment for the testing of any implementation of HPE and O3K Encoders. It is able to support a complete test campaign up to 100% of functional and code coverage. In addition, due to the full UVM compliance, it offers advantages in terms of reusability. The high efficiency of this Verification Environment leads to a substantial reduction in verification time and effort.