DOTTORATO DI RICERCA IN INGEGNERIA DELL'INFORMAZIONE

Foto 7

Links

Info for...

Login

Subscribe to this RSS feed

E. Rapuano, T. Pacini, L. Fanucci - "A Post-training Quantization Method for the Design of Fixed-Point-Based FPGA/ASIC Hardware Accelerators for LSTM/GRU Algorithms", Hindawi Computational Intelligence and Neuroscience journal, 11 May 2022

E. Rapuano, G. Meoni, T. Pacini,...G. Giuffrida, L. Fanucci: “An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study”, MDPI Remote Sensing journal, April 2021

C. Comino, T. Pacini, E. Rapuano: “Design and Implementation of an FPGA-based CNN hardware accelerator using Partial Reconfigurability: the CloudScout case study”, ApplePies 2021

G.Dinelli, G. Meoni, E. Rapuano, L. Fanucci : "Advantages and limitations of fully on-chip CNN FPGA-based hardware accelerator", IEEE International Symposium on Circuits And Systems (ISCAS), October 2020

G.Dinelli, G. Meoni, E. Rapuano, T. Pacini, L. Fanucci: "MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs", IEEE Journal on Emerging and selected Topics in Circuits And Systems (JETCAS), 2020

News

OFFERTA FORMATIVA A.A. 2024-2025

Subscribe to this RSS feed

Tel +39 050 2217511
PEC: This email address is being protected from spambots. You need JavaScript enabled to view it.

Dipartimento di Ingegneria dell'Informazione
P.I. 00286820501 - C.F. 80003670504

email: This email address is being protected from spambots. You need JavaScript enabled to view it.
Via G. Caruso - 56122 - Pisa