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E. Rapuano, T. Pacini, L. Fanucci - "A Post-training Quantization Method for the Design of Fixed-Point-Based FPGA/ASIC Hardware Accelerators for LSTM/GRU Algorithms", Hindawi Computational Intelligence and Neuroscience journal, 11 May 2022
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E. Rapuano, G. Meoni, T. Pacini,...G. Giuffrida, L. Fanucci: “An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study”, MDPI Remote Sensing journal, April 2021
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C. Comino, T. Pacini, E. Rapuano: “Design and Implementation of an FPGA-based CNN hardware accelerator using Partial Reconfigurability: the CloudScout case study”, ApplePies 2021
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G.Dinelli, G. Meoni, E. Rapuano, L. Fanucci : "Advantages and limitations of fully on-chip CNN FPGA-based hardware accelerator", IEEE International Symposium on Circuits And Systems (ISCAS), October 2020
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G.Dinelli, G. Meoni, E. Rapuano, T. Pacini, L. Fanucci: "MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs", IEEE Journal on Emerging and selected Topics in Circuits And Systems (JETCAS), 2020
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Prof. Franco Maria Nardini, Salvatore Trani, ISTI-CNR - Italy, "Challenges in Modern Web Search", 18-21 June 2024
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