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Elenco Pubblicazioni - Publications (1683)

Design of a hardware track finder (Fast Tracker) for the ATLAS trigger

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Abstract The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger and data acquisition system and will be even more so as contemporary collisions that…
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A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications

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Abstract In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks:…
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A pattern recognition mezzanine based on associative memory and FPGA technology for L1 track triggering at HL-LHC

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The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of…
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Avvenuti, M., Cresci, S., Del Vigna, F., & Tesconi, M. (2016). Impromptu Crisis Mapping to Prioritize Emergency Response. Computer, 49(5), 28-37.

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To visualize post-emergency damage, a crisis-mapping system uses readily available semantic annotators, a machine-learning classifier to analyze relevant tweets, and interactive maps to rank extracted situational information. The system was validated against data from two…
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N. Iardella, G. Nardini, G. Stea, A. Virdis, F. Mauro, D. Sabella, M. Caretti, G.M. Dell'Aera, "Coordinated scheduling in a Virtual-RAN prototype with OpenAirInterface", EUCNC 2016, Athens, 27-30 June 2016

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The virtualized Radio Access Network (V-RAN) is a key technology for 5G networks. In this paper we present a live prototype of Virtual RAN implementing a Coordinated Scheduling algorithm enforced by a centralized coordinator. The…
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