This paper presents the implementation of a state of charge (SOC) estimator for Lithium-ion battery in a Field Programmable Gate Array (FPGA) based System-in-the-Loop platform. The paper explains and provides results from alternative methods for accelerating the SOC calculations in the FPGA. The System-In-the-Loop (SIL) simulation provides a platform to develop a full FPGA-based BMS, using high-level tools to generate Hardware Description Language (HDL) code for the FPGA. The work has been developed into a reference design that is freely available and can be run on low-cost hardware. Results have been obtained for SOC calculation times for several alternative hardware implementations in the FPGA. The execution time to update one battery cell ranges from 44.9µs down to 16.5µs. The alternative methods allow a designer to choose a balance between calculation time and resource usage.
X.Tian, B. Jeppesen, T. Ikushima, F. Baronti and R. Morello, "Accelerating state-of-charge estimation in FPGA-based Battery Management Systems," 6th Hybrid and Electric Vehicles Conference (HEVC 2016), London, 2016, pp. 1-6.Written by ROCCO MORELLO
Published in Elenco Pubblicazioni - Publications