Sample rate conversion is a fundamental operation performed in the digital front-end of software-defined radio and all-digital receivers. Within this context, polynomial-based filters, such as the Farrow structure and its variants, are a sound solution when arbitrary resampling is required. This paper presents a design methodology and the results of the implementation on a field-programmable gate array (FPGA) device for a high-speed transposed Farrow structure based on a novel parallel architecture. The implemented architecture supported an input sample rate of up to 2.184 GHz with moderate utilization of the FPGA resources. Furthermore, signal-to-noise ratio and spurious-free dynamic range values higher than 87 dB and 98 dB were reported over a wide range of sample rate conversion factors. Our results may suggest an improvement in the tradeoff between flexibility, complexity and throughput compared with previous work in the field.

 

Keywords: {Sample rate conversion, software-defined radio, digital receiver, transposed Farrow structure, FPGA}

 

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