ATLAS is planning to use a hardware processor, the Fast Tracker (FTK), to perform on-line track reconstruction at the level−1 trigger event output rate (100 kHz). The processor can perform this task using a very large number of precalculated track patterns stored in a dedicated bank and processing those with a sufficient number of hits in a given event.
In order to obtain a better trade-off between the number of patterns and the number of fits needed to perform track reconstruction, FTK exploits variable resolution pattern matching. This is carried out by a dedicated device, the Associative Memory (AM) chip, which is inspired from ternary commercial Content Addressable Memory (CAM) and includes ternary logic. This architecture is able to employ the variable resolution feature in which the width of each pattern can be varied
layer by layer.
We have studied different methods of building the variable resolution pattern bank. We show how this new feature achieves the goal of having few enough patterns to fit in the hardware, while maintaining good efficiency and the required rejection against random combinations of hits for the luminosities and pileup conditions expected at the LHC after its Phase-I upgrades.

File: http://pos.sissa.it/archive/conferences/189/014/RD13_014.pdf