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Rainer Leupers, RWTH Aachen University - Germany, “Design Technologies for Embedded Multiprocessor Systems-on-Chip”, 14-17 july 2015

20 hours (5 credits)

Aula Riunioni del Dipartimento di Ingegneria dell'Informazione, Via G. Caruso 16, Pisa – Ground Floor

Short Abstract:
The trend towards Multicore and even Manycore architectures affects virtually all areas of computing today. Especially in the mobiles and consumer domains, an extremely high architectural efficiency (MIPS/Watt) is required. In order to manage the complexity of multi-billion transistor IC designs with dozens of heterogeneous processing engines, advanced Electronic System Level (ESL) tools are required. ESL can be roughly subdivided into four categories: architecture modeling and optimization, application SW mapping, simulation and verification, and efficient processing element design. After a general introduction to embedded MPSoC (Multiprocessor Systems-on-Chip) architectures and ESL technologies, the course will cover aspects from the above four domains, in particular SoC architecture exploration, embedded SW development with virtual platforms, efficient code generation for DSPs, and application-specific processing element design. The lectures will be complemented with hands-on lab sessions using modern industrial ESL tools. On the last day, a written final test will be offered.

Course Contents in brief:

  • Multiprocessor Systems-on-Chip
  • Electronic System Level Design
  • SoC architecture exploration and power estimation
  • Virtual Prototyping
  • Multicore programming tools
  • Application-specific processing elements (ASIPs)


  • Day1 (14.07.2015): 9.30-17.30
  • Day2 (15.07.2015): 9.30-17.30
  • Day3 (16.07.2015): 9.30-17.30
  • Day4 (17.07.2014): 9.30-11.00 – Final Test