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L. Pilato, S. Saponara and L. Fanucci, "Performance of digital adder architectures in 180nm CMOS standard-cell technology," 2016 International Conference on Applied Electronics (AE), Pilsen, Czech Republic, 2016

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In this paper, we present and compare the design and the performances of ten different implementations for a 16-bit adder in a 180nm CMOS standard-cell technology. Ripple carry adder, increment adder, triangle adder, uniform and progressive carry select adder, uniform and progressive carry bypass adder, conditional adder, ripple carry look ahead adder and hierarchical carry look ahead adder are taken into account. Every architecture is explained, highlighting the pros and cons. Finally, the results of area complexity, worst path timing and average power consumption for each implementation are shown.
Date of Conference: 6-7 Sept. 2016
Date Added to IEEE Xplore29 September 2016
ISBN Information:
Print ISSN: 1803-7232
Publisher: University of West Bohemia