In recent years, the information technology world have faced broad security issues due to the large amount of data flowing over the network. HW security solutions are often preferred in contexts where an high level of performance is required. Multiple HW implementation of the Advanced Encryption Standard can be found in literature. Although several optimization methods based on optimum composite field isomorphic mappings have been shown and evaluated, there is a lack of results coming from automatic synthesis tools. This work presents an optimization of the AES core using synthesis tools that exploits composite field arithmetic for the SBox module implementation. The Parametric syntheses are repeated for both FPGA technology, using Xilinx Vivado on a Xilinx Zynq 7000 board, and for Standard Cell technology, using Synopsys Design Compiler and 40nm CMOS Standard Cell libraries. Results highlight the discrepancies between analytic and synthesized optimum parameters.