This paper presents an optimized FPGA implementation of a binary image thinning algorithm. The reference thinning technique is based on iterated comparisons with a set of 48 3 x 3 binary masks. In the proposed architecture, the processing logic and the internal memory are implemented in a way that the comparison with a group of 8 masks on each 3 x 18 image segment can be done in parallel within a single clock cycle. This optimization entails a reduction of approximately 27 times in terms of execution cycles with respect to the relative software implementation. The algorithm was implemented on an ALTERA Stratix II EP2S15 FPGA. The resource occupation of the thinning block and the dedicated memory controllers is less than 9% at 100 MHz clock frequency. The target application required the elaboration of 360 x 288 images at 25 frames per second. The proposed solution produces the output in less than 20% frame period, allowing for further real-time processing.

Keywords: {binary image thinning, skeleton, FPGA}