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L. Benvenuti, A. Catania, M. Cicalini, A. Ria, M. Piotto and P. Bruschi, "A 0.3 V 15 nW 69 dB SNDR Inverter-Based Δ∑ Modulator in 0.18 μm CMOS," 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, Switzerland

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This paper presents an ultra-low voltage, ultra-low power, inverter-based, discrete-time delta sigma modulator. The modulator employs a novel, two-stage, switched capacitor integrator that overcomes most of the issues introduced by ultra-low voltage inverter-like amplifiers. The effectiveness of the proposed approach is demonstrated by means of electrical simulation performed on a circuit designed in UMC 0.18 μm CMOS technology. With a supply voltage of only 0.3 V, the modulator reaches an SNDR of 69.9 dB for a signal bandwidth of 80 Hz and a clock frequency of 20 kHz. Thanks to a power consumption of only 15.47 nW, this analog-to-digital converter is suitable for interfacing a wide variety of sensors in energy harvesting applications. Different bandwidth-power consumption trade-offs are possible by moderate increase of the power supply voltage.