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Dr. Matteo Andreozzi, Arm - United Kingdom - "Arm Architectures for High-Performance Real-Time"

Hours:
16 hours (4 credits)

Room:
Aula Riunioni del Dipartimento di Ingegneria dell’Informazione, Via G. Caruso 16, Pisa - Ground Floor

Short Abstract:

The evolution of computer systems is bringing them constantly closer to the physical world by making machines interact with their surrounding reality.  Industrial automation, robotics, aerospace and automotive industries drive increasing demands on both deterministic capabilities and compute performance into the Arm computer systems architecture.

This course will introduce elements of the Arm systems architecture and current and future solutions Arm is adopting, together with its partners, to enable the next generation of high-performance real-time computing.

The audience will be introduced to the Arm real-time compute activities, and how those activities will significantly impact all market segments where both performance and determinism are requirements.

Course Contents in brief:

  1. Introduction to Arm and the Arm Architecture
  2. System Architecture and Composition
  3. Heterogeneous multi-core platforms
  4. The shared resources interference problem in high performance real-time systems
    1. Shared caches
    2. Shared interconnect
    3. Shared memory
    4. Other: SMMU, accelerators, interrupt controller
  5. Introduction to modelling Heterogeneous platforms on gem5
  6. Introduction to Adaptive Traffic Profiles

Schedule:

Day 1 (half day)

  1. Introduction to Arm and the Arm Architecture
    1. History of Arm, current business models, markets, organization
    2. The concept of Arm Partnership and Ecosystem
    3. The Arm architecture: what is it, what is it for
  2. System Architecture and Composition
    1. Designing an Arm-based system, the role of the system architect
  3. Heterogeneous multi-core platforms
    1. Challenges and opportunities of next-generation compute platforms

Day 2 (full day)

  1. The shared resources interference problem in high performance real-time systems
    1. Shared caches
      1. Introduction to caches
      2. Points of contention, observability, controllability
  2. Shared interconnect
    1. Introduction to interconnects
    2. Points of contention, observability, controllability
  3. Shared memory
    1. Introduction to main memory
    2. Points of contention, observability, controllability
  4. Other: SMMU, accelerators, interrupt controller
    1. Overview of other shared resources, their characteristics and problematics

Day 3 (half day)

  1. Introduction to modelling Heterogeneous platform on gem5 and Adaptive Traffic Profiles
    1. The gem5 simulator
  2. Introduction to Adaptive Traffic Profiles
    1. ATP as a way to capture the dynamic behavior of memory devices