The design of low-phase-noise fully integrated frequency references is often a critical aspect in the development of low-cost integrated circuits for communication interfaces, sensing platforms, and biomedical applications. This work first discusses relaxation oscillator topologies and design approaches aimed at minimizing the phase noise; then, a single-comparator low-phase-noise RC relaxation oscillator is proposed, featuring a novel comparator self-threshold-adjustment technique.The oscillator was designed for a 10 MHz oscillation frequency. Electrical simulations performedon a 0.18 um CMOS design confirmed that the proposed technique effectively rejects the flicker component of the comparator noise, allowing for a 152 dBc/Hz figure of merit at a 1 kHz offset frequency. The standard deviation of the jitter accumulated across 10k oscillation cycles is lower than 4 ns. The simulated current consumption of the circuit is equal to 50.8 uA with a 1.8 V supply voltage. The temperature sensitivity of the oscillation frequency is also notably low, as its worst-case value across process corners is equal to -20.8 ppm/°C from -55 °C to 125 °C.
Keywords: relaxation oscillators; RC oscillators; phase noise reduction; low temperature sensitivity;low power; correlated double sampling; jitter modeling
